W5610 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n 32-bit risc microcontroller specifications are subject to change without notice, contact your sales representatives for the most update information. page 1 of 4 rev 1.0 jul.02 2007 W5610 brief sheet 32 bit risc micro processor
W5610 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n 32-bit risc microcontroller specifications are subject to change without notice, contact your sales representatives for the most update information. page 2 of 4 rev 1.0 jul.02 2007 1 features l cpu core C rdc s proprietary 32 bit risc architecture C 6 stage pipeline architecture C operation frequency: 166 mhz C supports a 16k-byte cache l parallel flash rom C supports 16-bit data bus width C parallel flash rom control interface up to 2m*16bits l sdram controller C supports 16-bit data bus width C sdram control interface up to 64mb l dma controller C provides two 8237 dma compatible controllers which are cascaded internally C 4 channels for 8-bit dma transfer and 3 channels for 16-bit transfer l interrupt controller C provides two 8259 compatible interrupt controllers which are cascaded internally C independent programmable level / edge-triggered interrupt channels l counter/timers C 8254 compatible timers C supports a watchdog timer (wdt) l high performance uart ports C supports 1 high performance uarts with send/receive 16-byte fifos C programmable baud rate generator C the data rates are programmable from 50 to 460.8k baud (max. to 1mbps) C the character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd or no parity, 5~8 data bits l rdc debug tool support C rdc debug tool with a jtag-like interface l general programmable i/o C 29 pins programmable i/o ports C pins individually configurable to input or output mode l two 10/100m fast ethernet mac ports C ieee 802.3u mii interface C ieee 802.3x flow control in full-duplex mode C internal loop-back self-test circuit support C descriptor architecture for packet tx/rx l wireless 802.11 a/b/g mac+bbp C 802.11 a/b/g standard compliant C 802.11 d/h/i/j standard compliant C dsss/cck modulation 1, 2, 5.5, 11 mbps C ofdm 6, 9, 12, 18, 24, 36, 48, 54 mbps C wep 64/128/256 bits C wpa, wpa2 C 802.1x supplicant C wifi wmm support l operating voltage range - core voltage: 1.8v 5% - i/o voltage: 3.3v 10% l ambient temperature: 0 ~ +70 c l package type - 208-pin pqfp
W5610 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n 32-bit risc microcontroller specifications are subject to change without notice, contact your sales representatives for the most update information. page 3 of 4 rev 1.0 jul.02 2007 2 block diagram
W5610 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n 32-bit risc microcontroller specifications are subject to change without notice, contact your sales representatives for the most update information. page 4 of 4 rev 1.0 jul.02 2007 3 package information 208-pin pqfp
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